SDI工程时钟路径分析

//------------- Receive Ports - RX Fabric Output Control Ports -------------
output rxoutclk_out,
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
input rxusrclk_in,
input rxusrclk2_in,//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
output txoutclk_out,//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
input txusrclk_in,
input txusrclk2_in, //----------------------------------------------------------//
//通过查阅x7gtx_sdi_wrapper.v文件中的k7gtx_sdi_wrapper_GT模块
k7gtx_sdi_wrapper_GT #(
.GT_SIM_GTRESET_SPEEDUP ("FALSE"))
GTX_i (
.rxusrclk_in (rx_usrclk),
.rxusrclk2_in (rx_usrclk),
.rxoutclk_out (rx_outclk), .txusrclk_in (tx_usrclk),
.txusrclk2_in (tx_usrclk),
.txoutclk_out (tx_outclk),
);//----------------------------------------------------------//
//检查rx_usrclk rx_outclk tx_usrclk tx_outclk的使用情况
//从k7gtx_sdi_wrapper_GT出来的tx_outclk和rx_outclk通过BUFG之后，
//变成了tx_usrclk和rx_usrclk后又进入了k7gtx_sdi_wrapper_GT模块
BUFG BUFGTX (
.I (tx_outclk),
.O (tx_usrclk));assign tx_usrclk_out = tx_usrclk;BUFG BUFGRX (
.I (rx_outclk),
.O (rx_usrclk));assign rx_usrclk_out = rx_usrclk;//tx_usrclk 驱动tx_usrclk_out,rx_usrclk驱动rx_usrclk_out
//tx_usrclk_out,rx_usrclk_out两个时钟通过x7gtx_sdi_wrapper模块输出
module x7gtx_sdi_wrapper #(
parameter FXDCLK_FREQ = , // Frequency, in hertz, of fixed frequency clock
parameter DRPCLK_PERIOD = , // Period of drpclk in ns, always round down
parameter PLLLOCK_TIMEOUT_PERIOD = , // Period of PLLLOCK timeout in ns, defaults to 2ms
parameter RESET_TIMEOUT_PERIOD = , // Period of GTH RESETDONE timeout in ns, defaults to 500us
parameter TIMEOUT_CNTR_BITWIDTH = , // Width in bits of timeout counter
parameter RETRY_CNTR_BITWIDTH = , // Width in bits of the retry counter
parameter CPLL_REFCLK_PORT = "REFCLK1", // Options are REFCLK0, REFCLK1, GREFCLK, NORTH0, NORTH1, SOUTH0, SOUTH1
parameter TX_CLK0_QPLL = , // Set to 1 if QPLL is TX serial clock source with tx_m = 0, else set to 0
parameter TX_CLK1_QPLL = , // Set to 1 if QPLL is TX serial clock source with tx_m = 1, else set to 0
parameter GT_SIM_GTRESET_SPEEDUP = "FALSE")
(
output wire rx_usrclk_out, // rxusrclk input
output wire tx_usrclk_out, // clock input
);//----------------------------------------------------------//
//对于SDI核来说rx_usrclk和tx_usrclk都是输入进SDI核的，而不是先前理解的
//从核里面输出的时钟rx_usrclk，tx_usrclk
smpte_sdi your_instance_name (
.rx_usrclk(rx_usrclk), // input wire rx_usrclk
.tx_usrclk(tx_usrclk), // input wire tx_usrclk
);//----------------------------------------------------------//
//对于x7gtx_sdi_control模块
//tx_usrclk和rx_usrclk作为时钟输入
x7gtx_sdi_control #(
.FXDCLK_FREQ (FXDCLK_FREQ),
.DRPCLK_PERIOD (DRPCLK_PERIOD),
.PLLLOCK_TIMEOUT_PERIOD (PLLLOCK_TIMEOUT_PERIOD),
.RESET_TIMEOUT_PERIOD (RESET_TIMEOUT_PERIOD),
.TIMEOUT_CNTR_BITWIDTH (TIMEOUT_CNTR_BITWIDTH),
.RETRY_CNTR_BITWIDTH (RETRY_CNTR_BITWIDTH),
.TX_CLK0_QPLL (TX_CLK0_QPLL),
.TX_CLK1_QPLL (TX_CLK1_QPLL))
GTX_CTRL (
.txusrclk (tx_usrclk),
.rxusrclk (rx_usrclk),
);//查看x7gtx_sdi_control模块代码
module x7gtx_sdi_control #(
parameter FXDCLK_FREQ = , // Frequency, in hertz, of fxdclk
parameter DRPCLK_PERIOD = , // Period of drpclk in ns, always round down
parameter PLLLOCK_TIMEOUT_PERIOD = , // Period of PLLLOCK timeout in ns, defaults to 2ms
parameter RESET_TIMEOUT_PERIOD = , // Period of GTH RESETDONE timeout in ns, defaults to 500us
parameter TIMEOUT_CNTR_BITWIDTH = , // Width in bits of timeout counter
parameter RETRY_CNTR_BITWIDTH = , // Width in bits of the retry counter
parameter TX_CLK0_QPLL = , // Set to 1 if QPLL is TX clock source when tx_m = 0, 0 otherwise
parameter TX_CLK1_QPLL = ) // Set to 1 if QPLL is TX clock source when tx_m = 1, 0 otherwise
(
// TX related signals
input wire txusrclk, // Connect to same clock as drives GTX TXUSRCLK2
// RX related signals
input wire rxusrclk, // Connect to same clock as drives GTX RXUSRCLK2
);//----------------------------------------------------------//
//再向上一层看
//x7gtx_sdi_wrapper模块输出rx_usrclk，tx_usrclk给其它模块使用module k7_sdi_rxtx #(
USE_CHIPSCOPE = "TRUE")
(
output wire rx_usrclk,
output wire tx_usrclk,
);multigenHD VIDGEN (
.clk (tx_usrclk),
);vidgen_ntsc NTSC (
.clk (tx_usrclk),
);vidgen_pal PAL (
.clk (tx_usrclk),
);x7gtx_sdi_wrapper #(
.FXDCLK_FREQ (),
.DRPCLK_PERIOD (),
.TIMEOUT_CNTR_BITWIDTH (), // 2^16 / 27e6 is enough for 2ms timeout period
.CPLL_REFCLK_PORT ("REFCLK1"), // CPLL reference clock connected to the gtrefclk1 port
.TX_CLK0_QPLL (), // TX uses QPLL as clock source when tx_m is Low
.TX_CLK1_QPLL ()) // TX uses CPLL as clock source when tx_m is High
SDI ( .rx_usrclk_out (rx_usrclk),
.tx_usrclk_out (tx_usrclk),
);