PCIE

在PCIe总线中，使用GT(Gigatransfer)计算PCIe链路的峰值带宽。GT是在PCIe链路上传递的峰值带宽，其计算公式为 总线频率×数据位宽×2。

在PCIe总线中，数据报文在接收和发送过程中，需要通过多个层次，包括事务层transaction（事务、学报、交易）、数据链路层和物理层。PCIe总线的层次结构如下。

1 PERST#信号全局复位信号

2 REFCLK+和REFCLK-信号 使用这组信号与处理器系统同步。

3 WAKE#信号  提交唤醒请求，使处理器系统重新为该PCIe设备提供主电源V_cc。

Virtex-7 FPGA Gen3
Integrated Block for
PCI Express v1.3

clock data recovery
(CDR) and differential signaling.

The key features of the Virtex-7 FPGA Gen3 Integrated Block for PCI Express (8.0 GT/s) core are:
• High-performance, highly flexible, scalable, and reliable, general-purpose I/O core
° Compliant with the PCI Express Base Specification, rev. 3.0
° Compatible with conventional PCI software model
• GTH transceivers
° 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s line speeds
° 1-lane, 2-lane, 4-lane, and 8-lane operation
• Endpoint configuration
• Multiple Function and Single-Root I/O Virtualization in the Endpoint configuration
° 2 Physical Functions
° 6 Virtual Functions
• Standardized user interface(s)
° Compliant to AXI4-Stream
° Separate Requester, Completion, and Message interfaces
° Flexible Data Alignment
° Parity generation and checking on AXI4-Stream interfaces
° Easy-to-use packet-based protocol
° Full-duplex communication enabling
° Optional back-to-back transactions to enable greater link bandwidth utilization
° Support for flow control of data and discontinuation of an in-process transaction in
transmit direction
° Support for flow control of data in receive direction
• Compliant with PCI and PCI Express power management functions
• Optional Tag Management feature
• Maximum transaction payload of up to 1024 bytes
• End-to-End Cyclic Redundancy Check (ECRC)
• Advanced Error Reporting (AER)
• Multi-Vector MSI for up to 32 vectors and MSI-X
• Atomic Operations and TLP Processing Hints

使用Gen3 X8

TLP:transaction layer packet

TLP Receiver Engine:
 This state machine receives TLPs from the PCI-e core and determines
their validity and destination.
 Controls register writes.
 Passes Read Completion payloads to the DDR3 DMA (if implemented).
 Passes BAR0, BAR2, or BAR4 register Read Requests to the TLP
transmitter engine.
TLP Transmitter Engine:
 Controls register Reads and constructs the resulting Read Completion
packets.
 Transmit Arbiter
 Provides arbitration for access to the PCI-e Core transmit data link port
for the eight ADC channel DMAs.
 Provides arbitration for access to the PCI-e Core transmit data link port
for register Read Completions.
 Provides arbitration for access to the PCI-e Core transmit data link port
for DDR3 DMA Read Requests (if implemented).
Memory Aperture Interface:
 Provides BAR and address decoding and the generation of chip selects.
 Creates BAR0, BAR2, and BAR4 register Write Data buses for
distribution throughout the FPGA.
 Creates 16 BAR0 register Read buses, 16 BAR2 user register Read buses,
and a FLASH device BAR4 Read bus for distribution throughout the
FPGA.
 It provides the multiplexing of the various data Read sources for
submission to the TLP transmitter engine.
PCI-e Control and Status Registers:
 It provides status of the PCI-e link including link width and speed.
 It provides the Interrupt Flag and Enable register that latches the various
interrupts from all of the other modules. Interrupts are combined to
generate an interrupt control to the PCI-e Core.
 Converts AXI-Lite Master accesses into standard PCI-e read/write
tranactions to provide AXI access to the Global Control Registers