NEXYS 3开发板练手--USB UART(二)

`timescale 1ns / 1ps
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// Company:
// Engineer:
//
// Create Date: 23:24:03 11/11/2013
// Design Name:
// Module Name: USB_UART
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module USB_UART(
clk,
data,
send,
tx,
busy,
led
); input clk,send;
input [:] data;
output reg tx,busy;
output [:] led; assign led = data;
//状态机状态定义
parameter Idel = 'b00,//空闲状态
Rdy = 'b01,//数据准备完成
LoadByte = 'b10,//数据传入
SendBit = 'b11;//数据发送 reg [:] BspClkReg;//波特率分频计数
reg BspClk;//波特率时钟 reg [:] tx_data;//发送的数据，加上起始位和停止位
reg [:] tx_byte_count;//发送位数计数 reg [:] state;//,next_state;//状态寄存器 //波特率分频模块，100M/10416
always@(posedge clk)
begin
BspClkReg <= BspClkReg + ;
if(BspClkReg == )
begin
BspClkReg <= ;
BspClk <= ~BspClk;
end
end always@(posedge BspClk)
begin
case(state)
Idel : begin
tx <= ;
busy <= ;
tx_byte_count <= ;
if(~send) state <= Rdy;
end
Rdy : begin
tx_byte_count <= ;
tx <= ;
busy <= ;
state <= LoadByte;
end
LoadByte : begin
tx_data <= {'b1,data,1'b0};
tx <= ;
busy <= ;
state <= SendBit;
end
SendBit : begin
tx <= tx_data[];
busy <= ;
tx_data <= tx_data >> ;
tx_byte_count <= tx_byte_count + ;
if(tx_byte_count == )
state <= Idel;
else
state <= SendBit;
end
endcase
end endmodule