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CPU Stepping
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步进
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步进（Stepping）是CPU的一个重要参数，也叫分级鉴别产品数据转换规范，“步进”编号用来标识一系列CPU的设计或生产制造版本数据，步进的版本会随着这一系列CPU生产工艺的改进、BUG的解决或特性的增加而改变，也就是说步进编号是用来标识CPU的这些不同的“修订”的。同一系列不同步进的CPU或多或少都会有一些差异，例如在稳定性、核心电压、功耗、发热量、超频性能甚至支持的指令集方面可能会有所差异。
目 录1步进
- 1.1 基本简述
- 1.2 定义
2检测方法
- 2.1 CPU-Z
- 2.2 S-Spec
3升级理由
- 3.1 处理器
- 3.2 晶元的重新划分
- 3.3 “小毛病”
- 3.4 制造工艺
- 3.5 升级好处
1步进
- 1.1 基本简述
- 1.2 定义
2检测方法
- 2.1 CPU-Z
- 2.2 S-Spec
3升级理由
- 3.1 处理器
- 3.2 晶元的重新划分
- 3.3 “小毛病”
- 3.4 制造工艺
- 3.5 升级好处
1步进基本简述
对于CPU制造商而言，步进编号可以有效地控制和跟踪所做的更改，也就是说可以对自己的设计、生产和销售过程进行有效的管理；而对于CPU的最终用户而言，通过步进编号则可以更具体的识别其系统所安装的CPU版本，确定CPU的内部设计或制作特性等等。步进编号就好比CPU的小版本号，而且步进编号与CPU编号和CPU ID是密切联系的，每次步进改变之后其CPU ID也可能会改变。一般来说步进采用字母加数字的方式来表示，例如A0，B1，C2等等，字母或数字越靠后的步进也就是越新的产品。一般来说，步进编号中数字的变化，例如A0到A1，表示生产工艺较小的改进；而步进编号中字母的变化，例如A0到B1，则表示生产工艺比较大的或复杂的改进。在选购CPU时，应该尽可能地选择步进比较靠后的产品。定义
“步进”的英文是Stepping，Intel的官方文档中将其表述为“Core Stepping，核心步进”。步进表示的含义是芯片因某种外在因素的变化而导致的物理或者电气特性的变化的产物。以Intel的处理器为例（下文都以Intel的处理器为例），Stepping的具体值是2-3位由数字和字母组成的字符串。常见的Intel处理器的步进值都是由“一位字母+一位数字”组成的：处理器的步进升级是属于升级中“最细微”形式。较之制程的升级，步进升级对周边硬件的要求是最低的。比如，90nm制程的处理器升级到65nm制程，刷新主板BIOS是必须的。但类似“A0到B0”的步进升级可以直接完成，无需任何额外的动作。2检测方法CPU-Z
那么如何查到一款处理器的步进值呢？最简单的方法是使用CPU-Z这款软件直接读取读取（可以在www.cpuid.com上下载到最新版的CPU-Z）：下载CPU-Z之后，将压缩包解压，直接双击CPU-Z.exe这个文件，稍等几秒钟之后，CPU-Z就会显示读取的处理器相关信息，其中就包括步进。S-Spec
CPU-Z的识别方法虽然准确，但有时候也有缺陷。比如，你的机器中只有较早版本的CPU-Z，可能会无法识别处理器，还有一种情况就是，CPU-Z必须在Windows环境下才能使用，如果身处CPU市场，周围都是盒装或是散装的处理器，怎么样才能快速识别步进呢？答案就是检验处理器表面的S-Spec，它的准确率也是100%。
上述这张图是一颗Core 2处理器表面的文字，第三行中，第二个字段“SL9SA”就是S-Spec号。由于S-Spec号都是以“SL”开头，也被称作SL号。SL号是识别处理器的重要依据，每一个SL号只对应某一特定频率，缓存，外频和步进的处理器。所以S-Spec号对处理器的分类是最精细的。处理器的任何一个参数发生变化都会引起SL号的变化。比如，都是E6300处理器，也会因为步进的不同而有不同的S-Spec号这就是以S-Spec号来识别步进的依据。提醒：S-Spec识别方法的缺陷是需要记忆，S-Spec与步进的对应关系需要在Intel的网站上才能查到，后文的附表提供了Intel已经发布的Core 2架构处理器的S-Spec号与核心步进的对应表。3升级理由我们看着CPU的步进一次次的改变，那么背后的变化又是什么呢？任何一款产品，从投产到最终产品寿命的终了，其制造工艺都是遵循着日益成熟的路径来走的。集成电路产品更是如此。一颗集成了几亿个晶体管的CPU，它的品质会因为制造工艺的逐步成熟而越来越好。处理器
在功能上进行简化是Intel调整处理器产品线的重要手段。比如，去掉对某些功能的支持就能诞生一个新型号的处理器：比如Pentium D 945和Pentium D 950，它们的主频，外频都是一致的，但是前者不支持VT技术，也就是说在功能上存在着缩水，在这种情况下，它们的步进必然是不同的。因为Intel完全可以通过改变工艺来控制新的用于封装Pentium D 945的晶元。晶元的重新划分
Intel会依据晶元的品质来决定给哪款处理器使用。但也存在着不同规格的晶元相互替换使用的情况。Core2中最典型的例子就是L2步进的使用。Core 2 E4300只有L2的步进，而同为2M缓存的E6300却有两种步进，一是L2，二是B2。因为早期的E6300使用的2M缓存是通过屏蔽掉Conroe核心4M缓存的一半实现的，这部分的E6300的步进与Conroe核心的E6600以及E6700保持一致；E4300出现之后，E6300也可以直接使用新的L2步进来制造，所以L2步进的E6300也出现在了Intel的文档中。“小毛病”
和软件一样，硬件的设计也不是一开始就完美无缺的。一颗处理器从tape-out到最终推向市场，会经历无数苛刻的系统测试，即便如此，有些细小的问题还是要到实际应用的时候才能发现的。对于在实际使用中发现的问题，Intel会推出新步进的处理器，解决一批已经发现的问题。所以，步进升级与软件的升级有异曲同工之妙。制造工艺
Intel的处理器制造工艺一直是处于不停的升级之中，但是这种升级未必是很大的改进，而是局部的，某些细节工艺的提升，这种情况也会使得Intel升级处理器的步进。比如Q6600四核处理器，就已经出现过B1，B2等多个步进，正式版的产品则为最新的B3步进，相比之下大部分Core 2双核处理器的制程仍然停留在B2步进上，因为相对于双核处理器，四核的Q6600处理器在工艺升级上的潜力更大。如果仔细的比较就会发现，步进实际上与某款特定型号的处理器无关，一款特定步进的晶元可以应用在多款处理器上，因此步进代表的其实是处理器制造工艺的某个阶段。比如两颗处理器Core 2 E6400和Core 2 E6700，它们的步进都是B2，这表示它们使用了相同的制造工艺。对于超频来说，这一概念是非常重要的：相同制程的处理器，应当具备接近的极限频率。升级好处
如前文所述，处理器制造工艺的逐步和硬件纠错是CPU步进提升的原因，尤其是前者，制造工艺的改进对我们的影响是最直接和最容易感受到的。通常来说，新步进处理器的超频能力更强，发热也会略低。庆幸的是，Intel不是按照步进来为处理器定价，我们能够买到的处理器都是以型号来划分价格的，如果两颗处理器的型号相同，但是步进有新有旧，你该选择谁呢？又怎么选呢？从超频的角度看，处理器升级步进的同时一半也会升级其超频能力，这其实是制造工艺的功劳。步进升级成效之一：超频能力有提高在处理器的架构没有发生重大变化的前提下，制程升级可以大幅度提高处理器的超频能力，最典型的例子就是90nm的Prescott Pentium4升级到65nm的CedarMill 核心的Pentium4。其实，不光是制程升级，处理器核心步进的升级也可以提高处理器的超频能力，只是幅度没有升级制程那样大而已。关于超频能力我们会在后文中详细探讨。步进升级变化之二：降低发热随着制造工艺的成熟和新工艺的采用，相同型号的处理器发热会随着制程的升级而降低。Pentium4是这个变化的典型代表。原本CedarMill核心的Pentium4处理器的TDP是86W，升级到最新的D0步进之后，处理器的TDP下降到了65W，这就已经达到了Core 2处理器的标准，大幅度提高了处理器的“每瓦性能”，显然采购这样的P4是最超值的，性能不降低的前提下，发热却小了很多。步进升级好处之三：处理器运行更稳定如果看看Intel处理器步进更新的勘误列表，就会发现原来一颗早期版本的处理器居然会有这么多的bug！即使是升级步进后，仍然会有新的问题不断的发现。虽然绝大多数普通用户在运行绝大多数应用中都很难遇到因为处理器的问题而造成的意外情况，但无疑，新制程的处理器会具备更强的稳定型和可靠性。4权威资料查找器
处理器规格查找器： 如何查找 sSpec 编号 （根据sSpec号，利用Intel处理器查找工具查询CPU的步进）处理器规格查找器工具旨在作为参考，帮助您查找英特尔处理器的技术指标信息。 要查找所需信息，您需要知道处理器的 sSpec 编号。sSpec 编号
sSpec 编号也称为技术指标编号和 SL 代码。 它是一个印在处理器上的 5 个字符的字符串（SL36W，XL2XL，等等），用来识别处理器。 您能够在处理器的标记上（参阅图 2）或者盒装处理器附带的标签上找到该编号。 以下面的图 1 作为示例，说明如何读取标签来查找您的 sSpec 编号。图 1：在盒装处理器标签上查找 sSpec 编号请注意： 当前，技术指标位于产品代码后，将来可能会有所改动。图 2： 在处理器标记中查找 sSpec 编号（两个示例）
请注意： 这些位置进行改动后，要获取特定处理器的 sSpec 编号的正确位置，请参阅处理器技术指标更新。找到 sSpec 编号之后，您就可以正确使用处理器规格查找器 工具。 http://en.wikipedia.org/wiki/Stepping_levelStepping levelFrom Wikipedia, the free encyclopedia The term stepping level in the context of CPU architecture or integrated circuitry is a version number.
Stepping level refers to the introduction or revision of the lithographic mask or masks within the set of plates that generate the pattern that produces the CPU or integrated circuit. The term derives from the name of the equipment ("steppers") that exposes the photoresist to light.[1]
Typically, when an integrated circuit manufacturer such as Intel or AMD invests money to do a stepping (i.e. a revision to the masks), they have found bugs in the logic, have made improvements to the design that allow for faster processing, or have found a way to increase yield or improve the "bin splits" (i.e. create faster transistors and hence faster CPUs). One result of some new steppings is that the CPU design is improved such that it overclocks better than others.[1]
Many CPUs have a means of interrogating them in order to discover their stepping level. For example, on x86 CPUs executing the CPUID with the EAX register set to '1' will place values in other registers that show the CPU's stepping level.
See also[edit]- Steppings of the Intel Core microarchitecture
http://en.wikipedia.org/wiki/Core_(microarchitecture)#Steppings
Steppings[edit]
The Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only represent incremental improvements but also different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips.
Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Additional steppings have been used in internal and engineering samples, but are not listed in the tables.
Many of the high-end Core 2 and Xeon processors use Multi-Chip Modules of two or three chips in order to get larger cache sizes or more than two cores.
Steppings using 65 nm process[edit]
Mobile (Merom) Desktop (Conroe) Desktop (Kentsfield) Server (Woodcrest,Clovertown, Tigerton) Stepping Released Area CPUID L2 cache Max. clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon B2 Jul 2006 143 mm² 06F6 4 MiB 2.93 GHz M5xx T5000 T7000L7000 E6000X6000 3000 5100 B3 Nov 2006 143 mm² 06F7 4 MiB 3.00 GHz Q6000QX6000 3200 5300 L2 Jan 2007 111 mm² 06F2 2 MiB 2.13 GHz T5000 U7000 E2000 E4000E6000 3000 E1 May 2007 143 mm² 06FA 4 MiB 2.80 GHz M5xx T7000 L7000X7000 G0 Apr 2007 143 mm² 06FB 4 MiB 3.00 GHz M5xx T7000 L7000X7000 E2000 E4000E6000 3000 Q6000QX6000 3200 5100 5300 7200 7300 G2 Mar 2009 143 mm² 06FB 4 MiB 2.16 GHz M5xx T5000 T7000L7000 M0 Jul 2007 111 mm² 06FD 2 MiB 2.40 GHz 5xxT1000 T2000T3000 T5000 T7000U7000 E1000 E2000 E4000 A1 Jun 2007 81 mm² 10661 1 MiB 2.20 GHz M5xx U2000 220 4x0
Steppings B2/B3, E1 and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4 MiB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the "Allendale" chips with just 2 MiB L2 cache, reducing production cost and power consumption for low-end processors.
The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express (Santa Rosa) platform with Socket P, while the earlier B2 and L2 steppings only appear for the Socket M based Mobile Intel 945 Express (Napa refresh) platform.
The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MiB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.
Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2.[6]
Steppings using 45 nm process[edit]
Mobile (Penryn) Desktop (Wolfdale) Desktop (Yorkfield) Server (Wolfdale-DP,Harpertown,Dunnington) Stepping Released Area CPUID L2 cache Max. clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon C0 Nov 2007 107 mm² 10676 6 MiB 3.00 GHz E8000 P7000 T8000 T9000P9000 SP9000 SL9000 X9000 E8000 3100 QX9000 5200 5400 M0 Mar 2008 82 mm² 10676 3 MiB 2.40 GHz 7xx SU3000 P7000 P8000 T8000SU9000 E5000E2000 E7000 C1 Mar 2008 107 mm² 10677 6 MiB 3.20 GHz Q9000QX9000 3300 M1 Mar 2008 82 mm² 10677 3 MiB 2.50 GHz Q8000Q9000 3300 E0 Aug 2008 107 mm² 1067A 6 MiB 3.33 GHz T9000 P9000 SP9000 SL9000Q9000 QX9000 E8000 3100 Q9000Q9000SQX9000 3300 5200 5400 R0 Aug 2008 82 mm² 1067A 3 MiB 2.93 GHz 7xx 900SU2000T3000 T4000SU2000SU4000 SU3000 T6000 SU7000 P8000SU9000 E3000 E5000E6000 E7000 Q8000Q8000SQ9000Q9000S 3300 A1 Sep 2008 503 mm² 106D1 3 MiB 2.67 GHz 7400
In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.
In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.
Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².[7] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).
CPU-Z
那么如何查到一款处理器的步进值呢？最简单的方法是使用CPU-Z这款软件直接读取读取（可以在www.cpuid.com上下载到最新版的CPU-Z）：
下载CPU-Z之后，将压缩包解压，直接双击CPU-Z.exe这个文件，稍等几秒钟之后，CPU-Z就会显示读取的处理器相关信息，其中就包括步进。
S-Spec
CPU-Z的识别方法虽然准确，但有时候也有缺陷。比如，你的机器中只有较早版本的CPU-Z，可能会无法识别处理器，还有一种情况就是，CPU-Z必须在Windows环境下才能使用，如果身处CPU市场，周围都是盒装或是散装的处理器，怎么样才能快速识别步进呢？答案就是检验处理器表面的S-Spec，它的准确率也是100%。
上述这张图是一颗Core 2处理器表面的文字，第三行中，第二个字段“SL9SA”就是S-Spec号。由于S-Spec号都是以“SL”开头，也被称作SL号。SL号是识别处理器的重要依据，每一个SL号只对应某一特定频率，缓存，外频和步进的处理器。所以S-Spec号对处理器的分类是最精细的。处理器的任何一个参数发生变化都会引起SL号的变化。比如，都是E6300处理器，也会因为步进的不同而有不同的S-Spec号这就是以S-Spec号来识别步进的依据。
提醒：S-Spec识别方法的缺陷是需要记忆，S-Spec与步进的对应关系需要在Intel的网站上才能查到，后文的附表提供了Intel已经发布的Core 2架构处理器的S-Spec号与核心步进的对应表。
3升级理由我们看着CPU的步进一次次的改变，那么背后的变化又是什么呢？任何一款产品，从投产到最终产品寿命的终了，其制造工艺都是遵循着日益成熟的路径来走的。集成电路产品更是如此。一颗集成了几亿个晶体管的CPU，它的品质会因为制造工艺的逐步成熟而越来越好。处理器
在功能上进行简化是Intel调整处理器产品线的重要手段。比如，去掉对某些功能的支持就能诞生一个新型号的处理器：比如Pentium D 945和Pentium D 950，它们的主频，外频都是一致的，但是前者不支持VT技术，也就是说在功能上存在着缩水，在这种情况下，它们的步进必然是不同的。因为Intel完全可以通过改变工艺来控制新的用于封装Pentium D 945的晶元。晶元的重新划分
Intel会依据晶元的品质来决定给哪款处理器使用。但也存在着不同规格的晶元相互替换使用的情况。Core2中最典型的例子就是L2步进的使用。Core 2 E4300只有L2的步进，而同为2M缓存的E6300却有两种步进，一是L2，二是B2。因为早期的E6300使用的2M缓存是通过屏蔽掉Conroe核心4M缓存的一半实现的，这部分的E6300的步进与Conroe核心的E6600以及E6700保持一致；E4300出现之后，E6300也可以直接使用新的L2步进来制造，所以L2步进的E6300也出现在了Intel的文档中。“小毛病”
和软件一样，硬件的设计也不是一开始就完美无缺的。一颗处理器从tape-out到最终推向市场，会经历无数苛刻的系统测试，即便如此，有些细小的问题还是要到实际应用的时候才能发现的。对于在实际使用中发现的问题，Intel会推出新步进的处理器，解决一批已经发现的问题。所以，步进升级与软件的升级有异曲同工之妙。制造工艺
Intel的处理器制造工艺一直是处于不停的升级之中，但是这种升级未必是很大的改进，而是局部的，某些细节工艺的提升，这种情况也会使得Intel升级处理器的步进。比如Q6600四核处理器，就已经出现过B1，B2等多个步进，正式版的产品则为最新的B3步进，相比之下大部分Core 2双核处理器的制程仍然停留在B2步进上，因为相对于双核处理器，四核的Q6600处理器在工艺升级上的潜力更大。如果仔细的比较就会发现，步进实际上与某款特定型号的处理器无关，一款特定步进的晶元可以应用在多款处理器上，因此步进代表的其实是处理器制造工艺的某个阶段。比如两颗处理器Core 2 E6400和Core 2 E6700，它们的步进都是B2，这表示它们使用了相同的制造工艺。对于超频来说，这一概念是非常重要的：相同制程的处理器，应当具备接近的极限频率。升级好处
如前文所述，处理器制造工艺的逐步和硬件纠错是CPU步进提升的原因，尤其是前者，制造工艺的改进对我们的影响是最直接和最容易感受到的。通常来说，新步进处理器的超频能力更强，发热也会略低。庆幸的是，Intel不是按照步进来为处理器定价，我们能够买到的处理器都是以型号来划分价格的，如果两颗处理器的型号相同，但是步进有新有旧，你该选择谁呢？又怎么选呢？从超频的角度看，处理器升级步进的同时一半也会升级其超频能力，这其实是制造工艺的功劳。步进升级成效之一：超频能力有提高在处理器的架构没有发生重大变化的前提下，制程升级可以大幅度提高处理器的超频能力，最典型的例子就是90nm的Prescott Pentium4升级到65nm的CedarMill 核心的Pentium4。其实，不光是制程升级，处理器核心步进的升级也可以提高处理器的超频能力，只是幅度没有升级制程那样大而已。关于超频能力我们会在后文中详细探讨。步进升级变化之二：降低发热随着制造工艺的成熟和新工艺的采用，相同型号的处理器发热会随着制程的升级而降低。Pentium4是这个变化的典型代表。原本CedarMill核心的Pentium4处理器的TDP是86W，升级到最新的D0步进之后，处理器的TDP下降到了65W，这就已经达到了Core 2处理器的标准，大幅度提高了处理器的“每瓦性能”，显然采购这样的P4是最超值的，性能不降低的前提下，发热却小了很多。步进升级好处之三：处理器运行更稳定如果看看Intel处理器步进更新的勘误列表，就会发现原来一颗早期版本的处理器居然会有这么多的bug！即使是升级步进后，仍然会有新的问题不断的发现。虽然绝大多数普通用户在运行绝大多数应用中都很难遇到因为处理器的问题而造成的意外情况，但无疑，新制程的处理器会具备更强的稳定型和可靠性。4权威资料查找器
处理器规格查找器： 如何查找 sSpec 编号 （根据sSpec号，利用Intel处理器查找工具查询CPU的步进）处理器规格查找器工具旨在作为参考，帮助您查找英特尔处理器的技术指标信息。 要查找所需信息，您需要知道处理器的 sSpec 编号。sSpec 编号
sSpec 编号也称为技术指标编号和 SL 代码。 它是一个印在处理器上的 5 个字符的字符串（SL36W，XL2XL，等等），用来识别处理器。 您能够在处理器的标记上（参阅图 2）或者盒装处理器附带的标签上找到该编号。 以下面的图 1 作为示例，说明如何读取标签来查找您的 sSpec 编号。图 1：在盒装处理器标签上查找 sSpec 编号请注意： 当前，技术指标位于产品代码后，将来可能会有所改动。图 2： 在处理器标记中查找 sSpec 编号（两个示例）请注意： 这些位置进行改动后，要获取特定处理器的 sSpec 编号的正确位置，请参阅处理器技术指标更新。找到 sSpec 编号之后，您就可以正确使用处理器规格查找器 工具。 http://en.wikipedia.org/wiki/Stepping_levelStepping levelFrom Wikipedia, the free encyclopedia The term stepping level in the context of CPU architecture or integrated circuitry is a version number.
Stepping level refers to the introduction or revision of the lithographic mask or masks within the set of plates that generate the pattern that produces the CPU or integrated circuit. The term derives from the name of the equipment ("steppers") that exposes the photoresist to light.[1]
Typically, when an integrated circuit manufacturer such as Intel or AMD invests money to do a stepping (i.e. a revision to the masks), they have found bugs in the logic, have made improvements to the design that allow for faster processing, or have found a way to increase yield or improve the "bin splits" (i.e. create faster transistors and hence faster CPUs). One result of some new steppings is that the CPU design is improved such that it overclocks better than others.[1]
Many CPUs have a means of interrogating them in order to discover their stepping level. For example, on x86 CPUs executing the CPUID with the EAX register set to '1' will place values in other registers that show the CPU's stepping level.
See also[edit]- Steppings of the Intel Core microarchitecture
http://en.wikipedia.org/wiki/Core_(microarchitecture)#Steppings
Steppings[edit]
The Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only represent incremental improvements but also different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips.
Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Additional steppings have been used in internal and engineering samples, but are not listed in the tables.
Many of the high-end Core 2 and Xeon processors use Multi-Chip Modules of two or three chips in order to get larger cache sizes or more than two cores.
Steppings using 65 nm process[edit]
Mobile (Merom) Desktop (Conroe) Desktop (Kentsfield) Server (Woodcrest,Clovertown, Tigerton) Stepping Released Area CPUID L2 cache Max. clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon B2 Jul 2006 143 mm² 06F6 4 MiB 2.93 GHz M5xx T5000 T7000L7000 E6000X6000 3000 5100 B3 Nov 2006 143 mm² 06F7 4 MiB 3.00 GHz Q6000QX6000 3200 5300 L2 Jan 2007 111 mm² 06F2 2 MiB 2.13 GHz T5000 U7000 E2000 E4000E6000 3000 E1 May 2007 143 mm² 06FA 4 MiB 2.80 GHz M5xx T7000 L7000X7000 G0 Apr 2007 143 mm² 06FB 4 MiB 3.00 GHz M5xx T7000 L7000X7000 E2000 E4000E6000 3000 Q6000QX6000 3200 5100 5300 7200 7300 G2 Mar 2009 143 mm² 06FB 4 MiB 2.16 GHz M5xx T5000 T7000L7000 M0 Jul 2007 111 mm² 06FD 2 MiB 2.40 GHz 5xxT1000 T2000T3000 T5000 T7000U7000 E1000 E2000 E4000 A1 Jun 2007 81 mm² 10661 1 MiB 2.20 GHz M5xx U2000 220 4x0
Steppings B2/B3, E1 and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4 MiB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the "Allendale" chips with just 2 MiB L2 cache, reducing production cost and power consumption for low-end processors.
The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express (Santa Rosa) platform with Socket P, while the earlier B2 and L2 steppings only appear for the Socket M based Mobile Intel 945 Express (Napa refresh) platform.
The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MiB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.
Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2.[6]
Steppings using 45 nm process[edit]
Mobile (Penryn) Desktop (Wolfdale) Desktop (Yorkfield) Server (Wolfdale-DP,Harpertown,Dunnington) Stepping Released Area CPUID L2 cache Max. clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon C0 Nov 2007 107 mm² 10676 6 MiB 3.00 GHz E8000 P7000 T8000 T9000P9000 SP9000 SL9000 X9000 E8000 3100 QX9000 5200 5400 M0 Mar 2008 82 mm² 10676 3 MiB 2.40 GHz 7xx SU3000 P7000 P8000 T8000SU9000 E5000E2000 E7000 C1 Mar 2008 107 mm² 10677 6 MiB 3.20 GHz Q9000QX9000 3300 M1 Mar 2008 82 mm² 10677 3 MiB 2.50 GHz Q8000Q9000 3300 E0 Aug 2008 107 mm² 1067A 6 MiB 3.33 GHz T9000 P9000 SP9000 SL9000Q9000 QX9000 E8000 3100 Q9000Q9000SQX9000 3300 5200 5400 R0 Aug 2008 82 mm² 1067A 3 MiB 2.93 GHz 7xx 900SU2000T3000 T4000SU2000SU4000 SU3000 T6000 SU7000 P8000SU9000 E3000 E5000E6000 E7000 Q8000Q8000SQ9000Q9000S 3300 A1 Sep 2008 503 mm² 106D1 3 MiB 2.67 GHz 7400
In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.
In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.
Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².[7] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).
查找器
处理器规格查找器： 如何查找 sSpec 编号 （根据sSpec号，利用Intel处理器查找工具查询CPU的步进）
处理器规格查找器工具旨在作为参考，帮助您查找英特尔处理器的技术指标信息。 要查找所需信息，您需要知道处理器的 sSpec 编号。
sSpec 编号
sSpec 编号也称为技术指标编号和 SL 代码。 它是一个印在处理器上的 5 个字符的字符串（SL36W，XL2XL，等等），用来识别处理器。 您能够在处理器的标记上（参阅图 2）或者盒装处理器附带的标签上找到该编号。 以下面的图 1 作为示例，说明如何读取标签来查找您的 sSpec 编号。
图 1：在盒装处理器标签上查找 sSpec 编号
请注意： 当前，技术指标位于产品代码后，将来可能会有所改动。
图 2： 在处理器标记中查找 sSpec 编号（两个示例）
请注意： 这些位置进行改动后，要获取特定处理器的 sSpec 编号的正确位置，请参阅处理器技术指标更新。
找到 sSpec 编号之后，您就可以正确使用处理器规格查找器 工具。
http://en.wikipedia.org/wiki/Stepping_level
Stepping levelFrom Wikipedia, the free encyclopedia The term stepping level in the context of CPU architecture or integrated circuitry is a version number.
Stepping level refers to the introduction or revision of the lithographic mask or masks within the set of plates that generate the pattern that produces the CPU or integrated circuit. The term derives from the name of the equipment ("steppers") that exposes the photoresist to light.[1]
Typically, when an integrated circuit manufacturer such as Intel or AMD invests money to do a stepping (i.e. a revision to the masks), they have found bugs in the logic, have made improvements to the design that allow for faster processing, or have found a way to increase yield or improve the "bin splits" (i.e. create faster transistors and hence faster CPUs). One result of some new steppings is that the CPU design is improved such that it overclocks better than others.[1]
Many CPUs have a means of interrogating them in order to discover their stepping level. For example, on x86 CPUs executing the CPUID with the EAX register set to '1' will place values in other registers that show the CPU's stepping level.
See also[edit]- Steppings of the Intel Core microarchitecture
http://en.wikipedia.org/wiki/Core_(microarchitecture)#Steppings
Steppings[edit]
The Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only represent incremental improvements but also different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips.
Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Additional steppings have been used in internal and engineering samples, but are not listed in the tables.
Many of the high-end Core 2 and Xeon processors use Multi-Chip Modules of two or three chips in order to get larger cache sizes or more than two cores.
Steppings using 65 nm process[edit]
Mobile (Merom) Desktop (Conroe) Desktop (Kentsfield) Server (Woodcrest,Clovertown, Tigerton) Stepping Released Area CPUID L2 cache Max. clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon B2 Jul 2006 143 mm² 06F6 4 MiB 2.93 GHz M5xx T5000 T7000L7000 E6000X6000 3000 5100 B3 Nov 2006 143 mm² 06F7 4 MiB 3.00 GHz Q6000QX6000 3200 5300 L2 Jan 2007 111 mm² 06F2 2 MiB 2.13 GHz T5000 U7000 E2000 E4000E6000 3000 E1 May 2007 143 mm² 06FA 4 MiB 2.80 GHz M5xx T7000 L7000X7000 G0 Apr 2007 143 mm² 06FB 4 MiB 3.00 GHz M5xx T7000 L7000X7000 E2000 E4000E6000 3000 Q6000QX6000 3200 5100 5300 7200 7300 G2 Mar 2009 143 mm² 06FB 4 MiB 2.16 GHz M5xx T5000 T7000L7000 M0 Jul 2007 111 mm² 06FD 2 MiB 2.40 GHz 5xxT1000 T2000T3000 T5000 T7000U7000 E1000 E2000 E4000 A1 Jun 2007 81 mm² 10661 1 MiB 2.20 GHz M5xx U2000 220 4x0
Steppings B2/B3, E1 and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4 MiB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the "Allendale" chips with just 2 MiB L2 cache, reducing production cost and power consumption for low-end processors.
The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express (Santa Rosa) platform with Socket P, while the earlier B2 and L2 steppings only appear for the Socket M based Mobile Intel 945 Express (Napa refresh) platform.
The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MiB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.
Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2.[6]
Steppings using 45 nm process[edit]
Mobile (Penryn) Desktop (Wolfdale) Desktop (Yorkfield) Server (Wolfdale-DP,Harpertown,Dunnington) Stepping Released Area CPUID L2 cache Max. clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon C0 Nov 2007 107 mm² 10676 6 MiB 3.00 GHz E8000 P7000 T8000 T9000P9000 SP9000 SL9000 X9000 E8000 3100 QX9000 5200 5400 M0 Mar 2008 82 mm² 10676 3 MiB 2.40 GHz 7xx SU3000 P7000 P8000 T8000SU9000 E5000E2000 E7000 C1 Mar 2008 107 mm² 10677 6 MiB 3.20 GHz Q9000QX9000 3300 M1 Mar 2008 82 mm² 10677 3 MiB 2.50 GHz Q8000Q9000 3300 E0 Aug 2008 107 mm² 1067A 6 MiB 3.33 GHz T9000 P9000 SP9000 SL9000Q9000 QX9000 E8000 3100 Q9000Q9000SQX9000 3300 5200 5400 R0 Aug 2008 82 mm² 1067A 3 MiB 2.93 GHz 7xx 900SU2000T3000 T4000SU2000SU4000 SU3000 T6000 SU7000 P8000SU9000 E3000 E5000E6000 E7000 Q8000Q8000SQ9000Q9000S 3300 A1 Sep 2008 503 mm² 106D1 3 MiB 2.67 GHz 7400
In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.
In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.
Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².[7] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).
From Wikipedia, the free encyclopedia
The term stepping level in the context of CPU architecture or integrated circuitry is a version number.
Stepping level refers to the introduction or revision of the lithographic mask or masks within the set of plates that generate the pattern that produces the CPU or integrated circuit. The term derives from the name of the equipment ("steppers") that exposes the photoresist to light.[1]
Typically, when an integrated circuit manufacturer such as Intel or AMD invests money to do a stepping (i.e. a revision to the masks), they have found bugs in the logic, have made improvements to the design that allow for faster processing, or have found a way to increase yield or improve the "bin splits" (i.e. create faster transistors and hence faster CPUs). One result of some new steppings is that the CPU design is improved such that it overclocks better than others.[1]
Many CPUs have a means of interrogating them in order to discover their stepping level. For example, on x86 CPUs executing the CPUID with the EAX register set to '1' will place values in other registers that show the CPU's stepping level.
See also[edit]- Steppings of the Intel Core microarchitecture
http://en.wikipedia.org/wiki/Core_(microarchitecture)#Steppings
Steppings[edit]
The Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only represent incremental improvements but also different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips.
Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Additional steppings have been used in internal and engineering samples, but are not listed in the tables.
Many of the high-end Core 2 and Xeon processors use Multi-Chip Modules of two or three chips in order to get larger cache sizes or more than two cores.
Steppings using 65 nm process[edit]
| Mobile (Merom) | Desktop (Conroe) | Desktop (Kentsfield) | Server (Woodcrest,Clovertown, Tigerton) | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Stepping | Released | Area | CPUID | L2 cache | Max. clock | Celeron | Pentium | Core 2 | Celeron | Pentium | Core 2 | Xeon | Core 2 | Xeon | Xeon |
| B2 | Jul 2006 | 143 mm² | 06F6 | 4 MiB | 2.93 GHz | M5xx | T5000 T7000L7000 | E6000X6000 | 3000 | 5100 | |||||
| B3 | Nov 2006 | 143 mm² | 06F7 | 4 MiB | 3.00 GHz | Q6000QX6000 | 3200 | 5300 | |||||||
| L2 | Jan 2007 | 111 mm² | 06F2 | 2 MiB | 2.13 GHz | T5000 U7000 | E2000 | E4000E6000 | 3000 | ||||||
| E1 | May 2007 | 143 mm² | 06FA | 4 MiB | 2.80 GHz | M5xx | T7000 L7000X7000 | ||||||||
| G0 | Apr 2007 | 143 mm² | 06FB | 4 MiB | 3.00 GHz | M5xx | T7000 L7000X7000 | E2000 | E4000E6000 | 3000 | Q6000QX6000 | 3200 | 5100 5300 7200 7300 | ||
| G2 | Mar 2009 | 143 mm² | 06FB | 4 MiB | 2.16 GHz | M5xx | T5000 T7000L7000 | ||||||||
| M0 | Jul 2007 | 111 mm² | 06FD | 2 MiB | 2.40 GHz | 5xxT1000 | T2000T3000 | T5000 T7000U7000 | E1000 | E2000 | E4000 | ||||
| A1 | Jun 2007 | 81 mm² | 10661 | 1 MiB | 2.20 GHz | M5xx | U2000 | 220 4x0 | |||||||
Steppings B2/B3, E1 and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4 MiB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the "Allendale" chips with just 2 MiB L2 cache, reducing production cost and power consumption for low-end processors.
The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express (Santa Rosa) platform with Socket P, while the earlier B2 and L2 steppings only appear for the Socket M based Mobile Intel 945 Express (Napa refresh) platform.
The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MiB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.
Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2.[6]
Steppings using 45 nm process[edit]
| Mobile (Penryn) | Desktop (Wolfdale) | Desktop (Yorkfield) | Server (Wolfdale-DP,Harpertown,Dunnington) | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Stepping | Released | Area | CPUID | L2 cache | Max. clock | Celeron | Pentium | Core 2 | Celeron | Pentium | Core 2 | Xeon | Core 2 | Xeon | Xeon |
| C0 | Nov 2007 | 107 mm² | 10676 | 6 MiB | 3.00 GHz | E8000 P7000 T8000 T9000P9000 SP9000 SL9000 X9000 | E8000 | 3100 | QX9000 | 5200 5400 | |||||
| M0 | Mar 2008 | 82 mm² | 10676 | 3 MiB | 2.40 GHz | 7xx | SU3000 P7000 P8000 T8000SU9000 | E5000E2000 | E7000 | ||||||
| C1 | Mar 2008 | 107 mm² | 10677 | 6 MiB | 3.20 GHz | Q9000QX9000 | 3300 | ||||||||
| M1 | Mar 2008 | 82 mm² | 10677 | 3 MiB | 2.50 GHz | Q8000Q9000 | 3300 | ||||||||
| E0 | Aug 2008 | 107 mm² | 1067A | 6 MiB | 3.33 GHz | T9000 P9000 SP9000 SL9000Q9000 QX9000 | E8000 | 3100 | Q9000Q9000SQX9000 | 3300 | 5200 5400 | ||||
| R0 | Aug 2008 | 82 mm² | 1067A | 3 MiB | 2.93 GHz | 7xx 900SU2000T3000 | T4000SU2000SU4000 | SU3000 T6000 SU7000 P8000SU9000 | E3000 | E5000E6000 | E7000 | Q8000Q8000SQ9000Q9000S | 3300 | ||
| A1 | Sep 2008 | 503 mm² | 106D1 | 3 MiB | 2.67 GHz | 7400 | |||||||||
In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.
In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.
Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².[7] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).
